Design and Analysis of FIR Filters using Distributed Arithmetic

5/27/2008 :: Walter Huang :: Ph.D. Topic Abstract

The objective of this research is to develop new hardware designs for finite impulse response filters using distributed arithmetic. What distinguishes this research from other similar research is the use of distributed arithmetic for both adaptive filtering and discrete-time analog filtering. In addition, the intention of this research is to expand the data available on the trade-off of using the proposed filtering structures versus traditional ones. The trade-offs that will be examined are throughput, area consumption, memory usage, and power utilization. For the digital designs, the level of hardware integration will include both field programmable gate array logic structures to synthesized VLSI layout. The analog filters will only be implemented as full custom VLSI layout.

Efficient Image Compression System with a CMOS Transform Imager

5/28/2008 :: Jungwon Lee :: Ph.D. Topic Abstract

This research is focused on the implementation of the efficient image compression system among the many potential application of this transform imager system. The implementation is performed based on both analog and digital design consideration. The baseline JPEG compression algorithm is implemented and tested to verify the functionality and performance of the transform imager system, and the computational reduction in digital processing is investigated. A novel wavelet-based embedded image compression algorithm using dynamic index reordering vector quantization (DIRVQ) is proposed for the system. Additional focus is placed on the efficient implementation of DIRVQ because of its intensive computational complexity, and highly efficient implementation is achieved without any performance compromise.

Physical Design Automation for Large Scale Field Programmable Analog Arrays

12/18/2006 :: Faik Baskaya :: Ph.D. Topic Abstract

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. However, FPAAs still have not achieved the same success as FPGAs in the digital domain even with the grown interest, availability and use of FPAAs. Although there have been general solutions proposed to handle a wide variety of architecture models, usually these design tools are not as efficient as techniques customized specifically for predefined architectures. The same idea applies to using FPGA design automation methods toward solving FPAA applications. Our goal in this research is to develop the first placement algorithm for large-scale floating-gate based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. A major source of parasitics introduced during the circuit mapping process is interconnect switches used for routing. Our goal is to obtain models of the mapped circuits that can be simulated using SPICE in order to observe the impact of interconnect parasitics on the relevant analog metrics. We also want to establish a benchmark suite consisting of different circuit classes and determine optimization metrics for each circuit class. Our initial results indicate that the mapped analog circuits obtain desired responses even with interconnect parasitics, clearly demonstrating the practicality of our modeling of FPAA. Finally, we aim to explore the given FPAA architecture for possible variations using device and interconnect models obtained. We acknowledge that such an effort requires a larger set of benchmark circuits, which will also be possible to build up as the given FPAA architecture evolves.

Physiologically Motivated Methods for Audio Pattern Classification

10/31/2006 :: Sourabh Ravindran :: Ph.D. Topic Abstract

Human-like performance by machines in tasks of speech and audio processing has remained an elusive goal. In an attempt to bridge the gap in performance between humans and machines there has been an increased effort to study and model physiological processes. However, the widespread use of biologically inspired features proposed in the past have been hampered mainly by either the lack of robustness across a range of signal-to-noise ratios or the formidable computational costs. In physiological systems, sensor processing occurs in several stages. It is likely the case that signal features and biological processing techniques evolved together and are complementary or well matched. It is precisely for this reason that modeling the feature extraction processes should go hand in hand with modeling of the processes that use these features. This research presents a front-end feature extraction method for audio signals inspired by the human peripheral auditory system. New developments in the field of machine learning and computational statistics are leveraged to build classifiers to maximize the performance gains afforded by these features. The structure of the classification system is similar to what might be expected in physiological processing. Further, the feature extraction and classification algorithms can be efficiently implemented using the low-power cooperative analog-digital signal processing platform. The usefulness of the features are demonstrated for tasks of audio classification, speech versus non-speech discrimination, and speech recognition. The low-power nature of the classification system makes it ideal for use in applications such as hearing aids, hand-held devices, and surveillance through acoustic scene monitoring.

Exploiting Floating-gate Transistor Properties in Analog Circuit Design

12/13/2005 :: Erhan Ozalevli :: Ph.D. Topic Abstract

In this research, floating-gate transistors are utilized to build reconfigurable/tunable, compact, and low-power circuits to be incorporated into signal processing applications. The analog storage feature of the floating-gate transistors is utilized to build a low-power and compact data converter. This feature and capacitive coupling capability are also employed to implement a reconfigurable finite impulse response (FIR) filter. Moreover, the tunability of resistive elements in CMOS technology is demonstrated by building highly linear tunable CMOS resistors. One of these resistors is integrated with highly linear amplifier and transconductance multiplier circuits to leverage the tunability into analog circuits. In summary, the objective of this research is to integrate the analog storage and capacitive coupling features of floating-gate transistors with analog circuits to implement reconfigurable/tunable, low-power, and compact circuits and systems.

Analog Signal Processing Using Floating-Gate Based Large-Scale Field-Programmable Analog Arrays

12/12/2005 :: Christoper Twigg :: Ph.D. Topic Abstract

To leverage the low power consumption of analog processing with the flexibility and precision of digital technology, a reconfigurable and programmable mixed signal prototyping and development platform needs to be explored. Although the digital side of this device has been thoroughly investigated and developed in the form of FPGAs, reconfigurable and programmable analog technologies in the form of FPAAs have lagged behind. By incorporating floating-gate transistors as the basic programmable element, a new class of large-scale FPAAs has been created which has the size and complexity needed to develop significant analog systems comparable to the digital systems being implemented in FPGAs today.

A Biologically Inspired Front End for Audio Processing Systems Using Programmable Analog Circuitry

12/8/2005 :: David Graham :: Ph.D. Topic Abstract

The object of this research is the development of a biologically inspired audio signal-processing system using programmable analog circuitry. The human cochlea efficiently decomposes any sound into its respective frequency components by harnessing the resonant nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this research consists of developing a filterbank composed of continuous-time, low-power, analog bandpass filters that will serve as the core front end to this silicon audio processing system. Like biology, the individual bandpass filters will be tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. In order to overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors will be used to precisely tune the time constants in the filters and to allow programmability of analog components.

Multi-Sensor Noise Suppression and Bandwidth Extension for Enhancement of Speech

12/2/2005 :: Dr. Rongqiang (James) Hu :: Ph.D. Topic Abstract

Speech enhancement has been an active research problem for decades and continues to be an important problem. This is made even more true by the proliferation of portable devices having audio input capabilities. In the presence of noise, both the quality and intelligibility of speech signals have been significantly deteriorated. Thus, to increase the performance of a speech processing system in real-world applications, a multi-sensor noise suppression system is proposed. Important side information from state-of-the-art non-air conductive sensors is utilized to drive a biologically inspired noise suppression algorithm and a glottal correlation filter in removing background noise. Also proposed is a speech bandwidth extension system that is used to extend to the wideband speech from the degraded speech acquired in the real-world, where the speech bandwidth is corrupted by background noise or transmission media.