Cooperative Analog and Digital Signal Processing : Georgia Institute of Technology  
About Us Key Technologies Research Projects Researchers Publications Topic Abstracts Teaching
group snapshot 2 group snapshot 1 group snapshot 3

Distributed Arithmetic Adaptive Filters

Abstract

The purpose of this research is to examine and establish alternative methods to implementing adaptive filters in hardware. The approach taken by this work is to utilize the parallelism found in distributed arithmetic (DA) filters. The throughput of DA filters is independent of filter size. As such, we construct an adaptive LMS FIR filter using DA methodologies. The concept was first refined and proven on an FPGA platform, and subsequently implemented on silicon with a custom IC solution.

Researchers

Daniel Allred
Walter Huang
Venkatesh Krishnan
Haw-Jing (Michael) Lo
Heejong Yoo

Adaptive Filters

  • Filters that can adapt to the changes in the signals they process
  • Applications include but are not limited to:
    • Echo cancellation
    • Channel equalization
    • Radar and sonar clutter rejection
  • State of the art implementations employ multiply and accumulate (MAC) units
  • Throughput of such methods is inversely proportional to filter size

Distributed Arithmetic for Fixed Filters

  • Very successful in implementing high throughput fixed filters for large filter sizes
  • Eliminates the need for hardware multipliers
  • Throughput is independent of filter size
  • Construct adpative filters using DA concept

Our Approach

We construct the DA-based adaptive LMS filter as shown:
DA diagram


Each Base Filter and Adaptation Unit is composed of the following: DA block
The memory DAFLUT contains the weights and all possible sums of the weights, and the memory DAALUT contains all possible combinations of sums of the most recent samples.

Status of Work

Completed

  • implemented and tested on Altera Stratix FPGA
  • designed and fabricated on TSMC 0.18um through MOSIS

In Progress

  • testing fabricated ASIC

References

  • D. J. Allred, H. Yoo, V. Krishnan, W. Huang, D. V. Anderson, "A novel high performance distributed arithmetic adaptive filter implementation on an FPGA," ICASSP, vol. 5, pp. V-161 - V-164
  • S. A. White, "Applications of distributed arithmetic to digital signal processing: A tutorial review," IEEE ASSP Magazine, vol. 6, pp. 4-19, July 1989.
  • C. H. Wei and J. J. Lou, "Multimemory block structure for implementing a digital adaptive filter using distributed arithmetic," IEEE Proceedings, vol. 133, Pt. G, no. 1, pp. 19-26, February 1986.
  • C. F. N. Cowan and J. Mavor, "New digital-adaptive filter implementation using distributed-arithmetic techniques," IEEE Proceedings, vol. 128, Pt. F, no. 4, pp. 225-230, August 1981.
This work is protected by a pending patent assigned to Georgia Tech Research Corporation.
Please contact kevin.wozniak [at] gtrc.gatech.edu for more information.
back to Research Projects